1. Field of the Invention
The present invention relates to a counter circuit comprising counters for generating a plurality of continuous pulses having different periodicities.
2. Description of the Prior Art
FIG. 12 shows a schematic diagram of a conventional counter circuit.
The counter circuit comprises an initial value register 1 for memorizing an initial value, a counter register 2 functioning as a counter, a count-up circuit 3 for outputting a count-up signal, and a control circuit 4 arranged between the initial value register 1 and the counter register 2.
When the counter register 2 is cleared to 0 by a reset signal, the initial value is written to the initial value register 1 by means of an unillustrated CPU. This initial value is a number from which the counter register 2 starts counting. When a clock pulse is fed to the counter register 2 and if the counter register 2 has a value of 0, then the initial value is written to the counter register 2 by means of a selector circuit 40 included in the control circuit 4. A comparator 41 detects whether or not an output value from the counter register 2 is 0. If the output value is not 0, then an arithmetic unit 42 deducts 1 from the output value and puts a resulting value back to the counter register 2 by means of the selector 40. In this way, once the initial value is written to the counter register 2, the value held thereby is decremented by 1 with every input of the clock pulse. When the value held by the counter register 2 becomes 0, then the count-up circuit 3 feeds out a count-up signal. Thereafter, the initial value is written to the counter register 2 again and an identical operation repeats. Continuous repetitions of this operation cause the count-up circuit 3 to output pulse signals having a period obtained by multiplying a period of the clock pulse by the initial value.
Conventionally, when many pulse signals having different periodicities are to be generated, counter circuits configured in such a way as described above should be arranged in a number equal to a number of the periodicities required and each different initial value should be written to the counter register 2 of each of such counter circuits.
However, using such counters circuit as described above necessitates a use of an identical number of counter circuits as the periodicities. Therefore, if a several thousands of pulse signals having different periodicities are to be generated, an equivalent number of counter circuits should be laid out, causing a huge area for mounting all of such circuits to be arranged.
To solve this problem, a timer multiplex circuit is suggested by Japanese Patent Application Laid-Open No. H03-085816. In this circuit, it is possible to reduce a circuit scale by sharing a timer circuit. According to this circuit, although it is possible to generate a plurality of interrupts having an identical period, it is difficult to generate a plurality of pulse signals each having a different periodicity because a timer period can not be set. According to a multi-stage hardware timer suggested by Japanese Patent Application Laid-Open No. H08-179998, it is possible to store a plurality of counter values by writing initial values to a RAM. However, once the initial values are written, count-up signals are fed out only once and accordingly, pulse signals are generated only once. As a result, it is impossible to generates a plurality of pulse trains having different periodicities.